Muhammad Faisal Siddiqui1, Abubakr Shafique2, Yousif Rauf Javed2, Talha Ahmad Khan2, Hamza Naeem Mughal2, Ahmed Wasif Reza1, Hammad Omer2, and Jeevan Kanesan1
1Electrical Engineering, University of Malaya, Kuala Lumpur, Malaysia, 2Electrical Engineering, COMSATS Institute of Information Technology, Islamabad, Pakistan
FPGA (Field Programmable Gate Array)
based application
specific hardware, for real-time Sensitivity Encoding (SENSE) reconstruction, embedded
on the receiver coil system may provide reconstruction without transferring the
data to the MRI server. This may dramatically decrease the transmission cost of
the system and the image reconstruction time. This paper proposes an FPGA
implementation of SENSE algorithm using two different sensitivity maps
estimation methods (pre-scan and E-maps). The results show that the
proposed system consumes only 145.64 μs for SENSE reconstruction (acceleration factor=2), while maintaining the quality of the reconstructed images with good
mean SNR (29+ dB) and significantly less artefact
power (<9×10-4) values.
