Recently gradient array systems draw attention of researchers with their capabilities. However, it is crucial to drive all array elements as desired to be able to spoil all the advantages of the gradient array. In terms of adjusting the timing of the gradient pulses, generating pulse width modulation (PWM) signals from one source, i.e. a single FPGA, for all array amplifiers would be a good solution. However, required number of bits to generate PWM signal would be limited to clock frequency. In this abstract, required digital resolution to generate PWM signals is analyzed and a method to generate PWM signals with resolution less than using I/O delay (IODELAY) elements of virtex7 family FPGA is presented.